This task is to implement the function F(A, B,C,D) = ACD e AB + BC) +ĀCD(BC + ABCD +ĀCD) in task2.vhd. Inputs: A, B, C, D Outputs: F, G, H 1. Create the task2.vhd file: a. Under “Flow Navigator” click “Add sources.” b. Select “Create or add design sources.” C. Click “Create File”, enter the file name “task2”, hit “OK”, and then click “Finish.” 2. A window will pop-up to define the port connections. All inputs and outputs above will be 1 bit in length 3. Simplify the equation above (call this output G) using Boolean algebra theorems and axioms and obtain the canonical SOP equation (call this output H). Write the code for all 3 equations (Fas the original equation above, G as the simplified equation (only use the theorems and axioms to simplify it, show all work), and the canonical SOP equation in H) in the architecture portion of your entity. Make sure you have all 3 equations as you will compare these later in simulation.