1. Describe all the mathematical equations involved in the Diffusion Capacitance model of a MOS Transistor with neat diagram. (CO1, 10M)
2. Consider the nMOS transistor in a 0.6 µm process with gate oxide thickness of 50 Å. The doping level is NA = 2 × 1019 cm–3 and the nominal threshold voltage is 0.6 V. The body is tied to ground with a substrate contact. How much does the threshold change at room temperature if the source is at 4 V instead of 0? (CO1, 5M)
3. The current in an enhancement mode NMOS transistor biased in saturation region was measured to be 2 mA at a drain source voltage of 2 V. When the drain source voltage was increased to 3 V while keeping gate source voltage same. The drain current increased to 3.03 mA. Use an appropriate drain current formula to calculate the channel length modulation parameter ? (Ignore the negative sign) (???? ??-1). (CO1, 5M)
4. Sketch a transistor-level schematic for a compound CMOS logic gate for each of the following functions: (CO2, 5 + 5 = 10 M)
a) Y = [AB + C · (A + B)]’ b) Y = [(A + B). (C + D)]’
