You are required to do a term research paper. Your task is to search and select a relatively new research topic or project (list of suggested topics below), you can also search and select recent research related to computer Architecture from one of the conferences and journals. Review research paper of the main topic selected with at least 3 relevant research papers as references. Use APA style, Minimum is 5 pages including the cover page and the reference page. (SafeAssign Enabled). If you select a project then the source code along with the documentation will be required. You can select either a review research paper or a Project but not both.
Project and Research Topics Ideas:
Code scheduling for ILP
Instruction/data Encoding
Cache-based enhancements (e.g., trace cache, filter cache, loop cache, victim cache,
stream buffers, etc.)
Pipeline clocking
Low power architectures
Quanitfying architectural characteristics of database workloads and comparing them to
other workloads
Achieve fault tolerance by running 2 copies of instructions in unused cycles in a
superscalar (e.g., a 4-way machine may commit less than 4 instructions due to
dependencies) and do instruction replication only in those cycles.
Use old register values to predict addresses of subsequent memory accesses. This allows
the pipeline to do the cache access early in the pipeline, avoiding load-use stalls.
By looking for phases in applications where fewer physical registers may suffice we can
cut down the amount of energy consumed by the register file.
Attempt to quantify how much of processor performance gain in the past decade has
come from faster clocks and how much from ILP.
Implement and compare victim caches and skewed-associative caches.
Implement and compare two recent prefetching schemes
Study prefetching methods (hardware and/or software) and their impact on performance
Evaluate cache behavior of networking (or other) applications or algorithms, with
modification to exploit caches and memory hierarchies
An implementation study of register renaming logic
In-order vs out-of-order superscalar processors
A study of dynamic branch prediction schemes for superscalar processors
An analysis of hardware prefetching techniques
The history and use of pipelining computer architecture
The effect of context switching on history-based branch predictors
Bounding worst-case performance for realtime applications
Branch prediction methods and performance
Performance of TLB implementations
Timing analysis and caching for realtime systems
A Survey of VLIW Processors
Evaluating Caches with Multiple Caching Strategies
Comparison Study of Multimedia-Extended Microprocessors
Synchronous DRAM
An Investigation of Instruction Fetch Behavior in Microprocessors
Register Renaming in Java Microprocessors
Optimizing Instruction Cache Performance with Profile-directed Code Layout
Power/Energy/Performance in a Branch Predictor of a Superscalar Processor
Workload Characterization of Network Processor Benchmarks
Dynamic Phase Behavior of Programs
Cache Miss Pattern and Miss Predictability Analysis
Low Power Cache Design
Analysis of Architecture Support for Virtual Machines
A Framework for Power Efficient Instruction Encoding in Deep Sub Micro Application Specific Processors
Cache Optimization for Signal Processing Applications
Design and Evaluation of Advanced Value Prediction Methods in Multi-Issue
Superscalar Pipelined Architectures
A New ISA to Efficiently Support Object-Oriented Programming (OOP) Paradigm
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