SOLUTION: VLSI Design Principles | My Assignment Tutor

YSGOL CYFRIFIADUREG A PHEIRIANNEG ELECTRONIGSCHOOL OF COMPUTER SCIENCE AND ELECTRONIC ENGINEERINGArholiadau Diwedd Semester 1End of Semester 1 Examinations2019/2020IES-2006VLSI Design PrinciplesAmser a ganiateir: 1½ awrTime allowed: 1½ hoursCyfarwyddiadau / Instructions:Answer all questions in Section A and any 2 from 3 in Section BTotal marks 50Trowch y dudalen drosodd pan ddywedir wrthych / Please turn over when instructed2IES-2006 VLSI Design Principles – ECE ParisSection A: answer all questions in this section. Total 30 marksA1. Types of ASICa) Describe, including simple diagrams, the basic features of full-custom ASICs, semicustom ASICs and FPGAs. Your description should include a discussion of the time ittakes to implement a working IC using each technology. [6]b) Give examples of products that would be best implemented using:i) an FPGAii) a full-custom ASICIn each case explain why your choice of technology is most suitable. [4]A2. Principles of Programmable ASIC Technologya) Explain how CMOS NAND and NOR gates can be generalised to yield more complexlogic cells such as so-called “AOI” and “OAI” cells. [2]b) Design the n-channel transistor stack for an AOI32 cell. [2]c) Design the p-channel stack for the cell. [2]d) Remembering that the electron mobility in silicon is typically two times as large as thehole mobility, determine the width-to-length ratios of all the transistors in the AOI32 cellto ensure it is at least as strong as a “1x” inverter. [4]A3. Principles of ASIC Designa) Explain how “implied memory” is used to describe synchronous storage in VHDL. [3]b) Write VHDL code to describe a synchronous state machine with one input “w” and oneoutput “z” which detects the sequence “001” on “w”. You may find it helpful to draw astate transition diagram first to capture the required behaviour. [7]3Section B: Answer 2 questions from 3 in this section. Total 20 marksB1. Principles of Programmable ASIC Technologya) Explain the key assumptions made in deriving the Elmore time constant whichapproximates the time delay between nodes in a circuit modelled by an RC tree. There isno need to derive the expression for the delay, which is:??? = ∑ ???????=1[4]b) Using the expression above for Di, find the time delay of ladder networks with one, twoand three stages of equal resistance R and capacitance C. Explain why this means thatinterconnections with many sections are best avoided in an FPGA. [6]B2. Principles of ASIC Designa) Describe how the principles of operator scheduling can lead to useful trade-offs of area(cost) and performance (speed) in designing complex digital systems. Your answershould describe how different operator scheduling decisions can lead to differentpositions in the Area-Time diagram of a system. [4]b) A high-level state machine requires the calculation of three products:t1 = t2 * t3t4 = t3 * t5t6 = t7 * t8Describe, with suitable diagrams, three different operator schedules for this set ofoperations. Explain, with reference to an area-time diagram how those different schedulesallow a trade-off between area and performance. [6]B3. Principles of ASIC DesignMetastability is a phenomenon which must be considered carefully when building sequentialcircuits.a) Describe, with a suitably-annotated timing diagram, how metastability upsets can occurin synchronous sequential systems. [4]b) Table B3.1 shows the characteristics of some flipflops from a number of FPGAmanufacturers. FPGAT0 / sc / sActel ACT 11.010–92.1710–10Xilinx XC3020-701.510–102.7110–10QuickLogic QL12x16-02.9410–112.9110–10Xilinx XC81002.1510-124.6510–10 Table B3.1 – T0 and c for a number of devicesIf the resolution time of the input flipflop to a system is fixed at 10ns, explain which of theFPGAs in table B3.1 would give the lowest probability of metastability upsets. [6]RCRCRCRCRCRC