# Calculating the small-signal voltage gain

1. A circuit in has (W/L)r= 42 tun/0.35 pm, (W/L)2=21 tun/0.7 pm, pc,Cox=200 pA/V2, PpCec=50 pAtV2, Ar 0.1 vd, A.= 0.2 Va, VDD=3.3 V, and bit= 0.3 mA when both devices are saturated. (a) Calculate the overdrive voltages (V8,) of MI and M2. (b)Calculate the small-signal voltage gain (VourN)24) (c) Calculate die maximum output swing while both devices are saturated.
2. In Fig. 2, assume(W/L)i=42 tun/0.7 pm , (W/L)2=21 pm/0.35 pm , mA, and RD=3.3 k12, Vrip3=0.7 V, tr,,C.=350 pA/V2, VDD=3.3 V, An=0.1. Neglect body effect. (a) Choose VB such that M1 is 50 mV away from the triode region (VDs2=Vosi-Vm+50mV, Mi operate in Saturation region), neglect a.. while calculating the bias point. (b) Calculate the small-signal voltage gain (VourNm). (c) Assume VB=2.2 V, calculate the maximum output voltage swing to keep all transistors in saturation. (d) Assume the maximum output swing is Voirr=1.5 Vpp, Calculate the swing at node X.
3. (a) Sketch the output voltage (Vora) and small-signal gain (Vour/Vm) roughly (without any calculation), of the folded-cascode stage shown in Fig. 3 (a) as VIII goes from 0 to Voo. Assume that the current source Iss is ideal. VB is the bias voltage which ensures both transistors are in saturation when IDI=ID2=1…/2. (b) Calculate the symbolic small signal (Vour/Var) gain of the folded-cascode stage shown in Fig. 3 (b) in terms of transistor parameters and the bias current Iss. Please note this circuit is the same with Fig 3 (a) except an ideal current source with ID=ISS/2 is replaced by RD. Neglect body effect. Assume all transistors are in saturation. Ignore channel-length modulation while calculating small signal parameters such as gm. (Hint: Try to draw the small signal model of the circuit to reach a straightforward solution.)
V00 M• V00 Voo RD V4> Van V00 Voo VOW VB MI Reg VoNT M VOWMg VB VN 2 V N x Mg 0X55 0155 Figure 1. Figure 2. Figure 3 (a). Figure 3 (b).

transistor size, resistance, and bias current given in Q1 to Q3. Use the 180 run CMOS technology library provided in Brightspace for the transistor parameters.)
4. (a) Build a test bench with the CS stage in Fig.1 using the parameters in Q 1 and plot the your-vs.-Vpi transfer curve using DC sweep simulation. (b) Find the small-signal voltage gains (slope of Vour-vs.-VIN) at Vour=0.7 V/2.7 V using the curve obtained in 4-(a). (c) Find the input voltage value (Vw) when the voltage gain is maximum using the curve obtained in 4-(a). (d) Find the output swing range when the voltage gain is still larger than 1 using the curve obtained in 4-(a). (e) Plot small-signal voltage gain (VourfVm) using AC sweep at Vour=0.7 V/2.7 V and compare the results with question 4-(b)
5. (a) Build a test bench with the cascode stage in Fig.2 and design a Vs value (please show reasoning and calculations) such that Mr is 100 mV away from the triode region, then plot Vour-vs.-Vni using DC sweep simulation. (Hint: You can start choosing a VB which makes Ml operating on saturation region. With the given condition Iniml5mA, we get Vas, through simulation, then use this V051 to design Vs.) b) Plot large-signal Icarr-vs.-Vour when VIN is fixed for 1131=0.5 mA using DC sweep simulation.
6. (a) From the large-signal lour-vs.-Vour curve in Q 5, derive the large-signal curve Rour-vs.- your using DC sweep simulation 6-(a) determine the Vous value when the output impedance is maximum.

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