Design a module named counter_101 using behavioral Verilog code. The module outp

Design a module named counter_101 using behavioral Verilog code. The module output count increases by 1 each time a sequence ‘101’ is detected on the input datain. Assume that datain is a 7-bit value. For example, if the input is ‘1010001’, the count value is 1. If the input is ‘1101010’, the count value is 2. 

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